1. Field of the Invention
The disclosure relates in general to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a semiconductor structure, comprising a step for forming a compensation layer.
2. Description of the Related Art
With a trend of shrinking a line width of a semiconductor process, a size of a semiconductor structure, comprising for example a MOS transistor or a memory array, etc., has been scaled down. However, an accurate process is necessary for obtaining a fine critical size of a semiconductor process. Otherwise, a semiconductor device would have a low efficiency resulted from a process shift or a side effect in a manufacturing step.